1. Technical Field
The present invention relates generally to content addressable memories. More particularly, the present invention provides a method and system for testing content addressable circuitry and associated word line driver circuitry.
2. Description of Related Art
With the increasing number of applications for computer systems, the demand for computer systems continues to expand. To meet the increasing demand and expanding customer base, computer systems have been provided with ever increasing performance characteristics. The increasing speed of central processing units or CPUs is very apparent. However, to take maximum advantage of the faster CPUs, the other basic computer subsystems must also be constantly improved to be capable of running at the higher system speeds. Moreover, increasing application complexities have also placed greater demands on computer subsystems so that the computer systems not only run at faster speeds but also are capable of handling much more complex applications and data handling requirements.
In computer systems, cache memory subsystems have become a critical area for improvement. More specifically, wordline driver circuits, which control the memory cells in cache arrays, have not undergone many changes. In the past, wordline drivers were simple and straightforward because caches were simple and there were fewer operations implemented in the cache. With more powerful, faster and more complex microprocessors, cache subsystems and wordline driver circuits must also be improved to make optimum use of the increased CPU capabilities. For most applications, the size and speed of the cache circuitry must be improved to allow greater amounts of programming and data to be available for even faster access by the CPU in running modern complex computer applications. As bandwidths increase, however, timing problems may be created, which in some cases may be sufficiently severe to affect the reliability of the circuit. Thus, there is a need for an improved cache subsystem and cache controlling circuitry in order to provide even greater cache capabilities for modern computer system applications.
A content addressable memory (CAM, or xe2x80x9cassociative memoryxe2x80x9d), a kind of storage device which includes comparison logic with each bit of storage, represents one such improvement. A data value is broadcast to all words of storage and compared with the values there. Words that match are flagged in some way. Subsequent operations can then work on flagged words, e.g. read them out one at a time or write to certain bit positions in all of them. CAMs are often used in caches and memory management units.
Word line drivers are well known in the prior art, for instance, the application entitled: xe2x80x9cA DYNAMIC WORD DRIVER FOR CACHExe2x80x9d, Manoj Kumar, et al, U.S. application Ser. No. 09/024,806, filed on Feb. 17, 1998, now U.S. Pat. No. 6,122,710, which is incorporated herein by reference in its entirety. A word line driver is an integral part of a CAM array. The comparison logic feeds match information into the word line drivers for the array. When a particular word line driver goes high, the array is read or written from the storage cells associated with that word line. When a particular word line driver is low then the storage cell in the array associated with that word line driver cannot be accessed.
Heretofore, the overhead requirements associated with the addition of onboard testing circuitry for testing individual word lines has been prohibitive. Generally chips are tested prior to shipment to the customer by manually invoking patterns. If the expected values are output from the pattern, the entire chip is assumed to be in working condition. If, on the other hand, a chip fails the test, further diagnosis is usually limited because of the lack of onboard testing capabilities. More importantly, because the testing has been limited to invoking manual patterns, it was impossible to perform systems tests at system start up time. The problem of limited space is exacerbated by the number word lines needed for servicing a CAM, wherein duplicative testing circuits are needed for testing each word line.
Therefore, it would be advantageous to incorporate onboard circuitry for testing the operations of the individual content addressable memories. It would be further advantageous to incorporate onboard circuitry for testing the operations of the individual word line driver circuits. It would still further be advantageous to provide such testing circuitry with the addition of minimal overhead. The present invention addresses these problems directly.
The present invention discloses a match word line driver circuit that operates in two modes, functional and test. Each match word line driver circuit associated with a content addressable memory (CAM) utilizes a scannable latch for testing. The scannable latches associated with a particular CAM are connected together, scan output of one to scan input of the next, forming a scanning latch chain. In test mode the scannable dynamic latch is used either for testing CAM match circuits or for driving word lines to test the RAM array. Testing CAM match circuits is accomplished by patterning the CAM array with known storage values. The match circuitry then compares an effective address to each storage value and the results are scanned out. Testing the RAM array is performed by driving each word line with a known scan value. Each word line responds the scan value and a sense amplifier outputs a RAM array value based on the word line.